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Preliminary Program

08.06.2015

08:30 Welcome and Opening Remarks
09:00 - 10:00 Keynote Speaker: Gernot Spiegelberg 
10:00 - 10:30 Coffee Break
Session 1 Automotive Systems
10:30 - 12:00 ReSA: Ontology-based Requirement Specification Language Tailored to Automotive Systems
Efficient Compositing Strategies for Automotive HMI Systems
TTEthernet SW-based End System for AUTOSAR
12:00 - 13:30 Lunch
Session 2 Architectures and architecture analysis
13:30 - 15:30 Real-Time DRAM Throughput Guarantees for Latency Sensitive Mixed QoS MPSoCs
WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness
Periodic Thermal Management for Hard Real-time Systems
Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores
15:30 - 16:00 Coffee Break
Session 3 Networked embedded systems
16:00 - 18:00 Analysis of access control policies in networked embedded systems: a case study
A New Profibus-DP Intelligent Slave Interface for CERN’s Sputter Ion Pump Controllers
Real-time Network Traffic Handling in FASA
Stochastic Delay Analysis of a Wireless Safety-Critical Avionics Network

09.06.2015

08:30 Registration
09:00 - 10:00 Keynote Speaker: Hermann Kopetz
10:00 - 10:30 Coffee Break
Session 4 Time-triggered systems and Cyclic executives
10:30 - 12:00 Time-Triggered Communication Scheduling Analysis for Real-Time Multicore Systems
Supporting Firm Real-Time Traffic in Fault-Tolerant Real-Time Systems based on Cyclic Scheduling - The WICKPro Protocol
Building an Interactive Test Development Environment for Cyclic Executive Systems
12:00 - 13:30 Lunch
Session 5 WIP session
13:30 - 15:30 Monitoring of I/O for Safety-Critical Systems Using PCI Express Advanced Error Reporting
Energy- and Latency-Aware Simulation of Battery-Operated Wireless Embedded Networks for Home Automation
Fail-Operational in Safety-Related Automotive Multicore Systems
A Framework Architecture for Student Learning in Distributed Embedded Systems
Virtual prototyping of heterogeneous dynamic platforms using Open Virtual Platforms
Optimal SAT-based Scheduler for Time-Triggered Networks-on-a-Chip
SMT-based Synthesis of TTEthernet Schedules: a Performance Study
A Model-Based Workflow from Specification Until Validation of Timing Requirements in Embedded Software Systems
Protecting FPGA-based Automotive Systems against Soft Errors through Reduced Precision Redundancy
Semi-online Power Estimation for Smartphone Hardware Components
15:30 - 16:00 Coffee Break
Session 6 Resource Management and Real-Time Scheduling
16:00 - 17:30 Deriving Period Restrictions from a Given Utilization Bound under RMS
From Modes to Patterns: pattern-based resource management in time-critical applications
Resource Sharing Under Global Scheduling with Partial Processor Bandwidth
18:00 Social Event

10.06.2015

08:30Registration
09:00 - 10:00 Keynote Speaker: Alfons Crespo
10:00 - 10:30 Coffee Break
Session 7 Operating Systems, Virtualization and Hypervisors
10:30 - 12:00 Extended Support for Limited Preemption Fixed Priority Scheduling for OSEK/AUTOSAR-Compliant Operating Systems
Integrating Linux and the real-time ERIKA OS through the Xen hypervisor

Mapping CAN-to-Ethernet Communication Channels within Virtualized Embedded Environments

12:00 - 13:30 Lunch
Session 8 Analysis and Synthesis by Formal Methods
13:30 - 15:30 A Formal, Model-driven Design Flow for System Simulation and Multi-core Implementation
Using BIP to reinforce correctness of resource-constrained IoT applications
Model Checking of Finite-state Machine-based Scenario-aware Dataflow Using Timed Automata
A formal approach for the synthesis and implementation of fault-tolerant industrial embedded systems