SAFE4RAIL

Fundamentally simplified TCMS platform – provide a baseline for a simplified embedded computing and networked Train Control and Monitoring System (TCMS) for modular integration and certification of safety‑critical, time‑critical and mission‑critical train functions up to SIL4. The generic platform will support mixed‑criticality integration and virtualization on reconfigurable computing and networking resources and demonstrate the concept with a SIL4 brake‑by‑wire system

Projectdescription

Safe4RAIL proposes safety concepts for mixed‑criticality Ethernet‑based networking and a mixed‑criticality application framework. The project combines cross‑industry best practices, models of computation and embedded platform technologies to develop proof‑of‑concepts that demonstrate core components of an integrated modular TCMS architecture. It includes a simulation and testing environment based on hardware abstraction and domain separation to enable early functional integration testing and to validate the brake‑by‑wire concept.

Focus points/areas

Mixed-criticality TCMS platform with deterministic Ethernet to enable modular certification (SIL4 brake-by-wire).

Links

EU Project

Research Goals

1. Configurable mixed‑criticality networking (“Drive‑by‑Data”) concept

-assess deterministic Ethernet standards from other transport sectors, host all system traffic with different timing and safety requirements and design a concept and methodology for railway network and embedded platform integration.

2. Mixed‑criticality application framework

– provide solutions for functional safety‑critical and non‑critical requirements, analyse viability of existing embedded platforms (AUTOSAR/MICROSAR, ARINC 653, TRDP) and design a methodology with proof‑of‑concept implementations.

3. Simulation and testing environment

– develop a network‑centric system‑level simulation with timing‑accurate models, support Software‑in‑the‑Loop (SIL) and Hardware‑in‑the‑Loop (HIL) testing, co‑simulation with remote subsystems and simulate wireless interfaces.

4. Brake‑by‑wire architecture and safety concept

– move train brake controls to a fully electronic brake‑by‑wire system, define safety communication requirements, develop hardware/software safety architecture with redundancy and proof‑of‑concept, and define verification and validation processes.

5. Modular certification capability

– facilitate partition‑level development, migration and re‑certification and demonstrate interference‑freeness of the functional distribution architecture.

6. Contribution to safety and technology standards –

identify gaps in current standards and provide recommendations for embedded platform and networking capabilities not covered by existing safety standards (e.g., IEC 61375, EN 5012x, EN 50657)

Methodology

Safe4RAIL starts from cross‑industry best practices, computation models and embedded platform technologies, drawing on experience from aerospace and automotive sectors. It analyses deterministic Ethernet and existing application frameworks to design a generic, mixed‑criticality platform. Proof‑of‑concept implementations are developed to demonstrate the core components, with a focus on hardware abstraction, domain separation and virtualization so that applications can be tested and integrated long before vehicle integration. The project also creates a network‑centric simulation and testing environment that enables Software‑in‑the‑Loop and Hardware‑in‑the‑Loop testing, including co‑simulation across different sites. Finally, Safe4RAIL validates its methodology through a brake‑by‑wire demonstration and formulates recommendations for modular certification and future standards

Das Projektteam

Univ.-Prof. Dr.-Ing. Roman Obermaisser

Professor

Prof. Dr. Roman Obermaisser is full professor at the Division for Embedded Systems of University of Siegen. Roman Obermaisser has finished his doctoral studies in Computer Science with Prof. Hermann Kopetz at Vienna University of Technology as research advisor in 2004.

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Dr.-Ing. Daniel Lucky Ndubuisi Onwuchekwa

Research assistant

daniel.onwuchekwa@uni-siegen.de

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